www.design-reuse.cn
搜索,选择,比较,与提供商进行安全高效的联系
Design & Reuse We Chat

受益于Synopsys设计及验证方案,Astera Labs得以开发业界首款PCIe 5.0 Retimer SoC

Synopsys Design and Verification Solutions Enable Astera Labs to Develop Industry's First PCIe 5.0 Retimer SoC

May. 30, 2019 – 

Industry's First Full-chip Implementation and Verification Completed Entirely on Amazon Web Services Cloud

MOUNTAIN VIEW, Calif. -- Synopsys, Inc. (Nasdaq: SNPS) today announced that Astera Labs successfully utilized Synopsys' Fusion Design Platform, Verification Continuum Platform, and Design Services to develop its breakthrough connectivity technology for next-generation servers, all running on Amazon Web Services (AWS). The collaboration represents two game-changing industry milestones: the first large-scale design fully implemented and verified from start to finish on a third-party public cloud, and the industry's first PCIe 5.0 retimer for heterogenous compute and workload-optimized servers.

"At Astera Labs, we are intensely focused on delivering high-quality solutions to our customers. We collaborated with Synopsys, a leader in EDA tools and PCIe technology, to ensure our products meet PCIe Gen-5 specifications and are geared for high-volume manufacturing," said Jitendra Mohan, chief executive officer at Astera Labs. "Our High-Performance Compute (HPC) infrastructure is hosted entirely on AWS and we heavily leveraged the scale of AWS and the cloud-scalability of Synopsys tools to accelerate our development schedule."

"We are excited to collaborate with Synopsys, a market leader in chip design and verification software. Together, we are providing groundbreaking cloud solutions for our mutual semiconductor customers, which represent a significant milestone, creating smart products and devices for solutions involving IoT, machine learning, artificial intelligence, and big data," said Terry Wise, vice president, Channels and Alliances, Amazon Web Services, Inc. "By leveraging the power of AWS, Synopsys is able to further semiconductor innovation and help Astera Labs reduce time-to-results."



PCIe 5.0 IP Cores

"In our collaboration with industry leaders and our ecosystem, we continue to work closely with innovators to enable next-generation designs with a broad and complete solution," said Deirdre Hanford, co-general manager of the Design Group at Synopsys. "Our collaboration with pioneers such as Astera Labs breaks new ground in what can be achieved in combining leading EDA technology and cloud computing."

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Synopsys Design and Verification Solutions Enable Astera Labs to Develop Industry's First PCIe 5.0 Retimer SoC

 Back

业务合作

访问我们的合作伙伴页面了解更多信息

广告发布

访问我们的广告选项

添加产品

供应商免费录入产品信息

© 2018 Design And Reuse

版权所有

本网站的任何部分未经Design&Reuse许可,
不得复制,重发, 转载或以其他方式使用。