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VisualSim Processor Generator is a revolutionary and extremely intelligent library. The library contains the generators and a large set of pre-defined components. This VisualSim Artificial Intelligence (AI)-driven Processor Generator is used for performance analysis and architecture exploration of System-on-Chip (SoC) and Embedded Systems. The generated model is pipeline-accurate and has port integration with standard buses and memories. This processor model is used to compare different processor families, optimize the specification and identify system bottlenecks. The AI Processor Generator currently supports microcontrollers, microprocessor, DSP and GPUs. The breath of processors can range from 8-bit to 128-bit and none to 4 level caches

Selecting the right processor, configuring multi-cores and establishing the right topology is very challenging for complex systems. Acquiring boards and loading software on each processor instance is expensive; emulators, RTL and cycle-accurate models take a long time to simulate and are not easily available; virtual prototypes do not provide timing accuracy; while analytical models cannot handle the complex traffic patterns. AI technology has evolved to enable this library to take a spreadsheet input and generate a processor model that is fast, accurate and visual.

Mirabilis Design has used Artificial Intelligence to identify patterns in over 100 processors. Using these patterns, VisualSim AI Processor Generator has created a unique input spreadsheet. Using this input and the learning algorithm database loaded into the generator, existing and future processors models are generated. Data for the input spreadsheet is available in the vendor datasheet. The generated model supports variable processor pipelines, SIMD/MIMD, multi-thread, multi-level cache hierarchy, coherency, heterogeneous execution units, buffers and bus interfaces. The generated model has over 150 statistics for cache hit-ratio, stalls and utilization. The processor has probes to trace pipeline execution sequence, prefetch requests, interrupts and preemption.


  • Generator of RISC, CISC, Micro-Controllers
  • Spreadsheet-based
  • Defines timing, power and functionality
  • Multiple stage pipeline
  • Multi-level cache and memory hierarchy
  • Supports multiple interfaces
  • DMA support
  • Changing the Clock Speed- Used when a specific operation or the stage of the pipeline needs to be expanded.
  • Using multi cycle delay for the flush from annotate C-code
  • Preemption Enabled Adding preemption to the Processor








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