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Short Description

Cadence Innovus 实施系统针对业界领先的嵌入式处理器进行了优化,帮助您在更早的设计阶段加快设计速度。


The Cadence® Innovus™ Implementation System is optimized for industry-leading embedded processors, as well as for 16nm, 14nm, 10nm, and 7nm processes, helping you get an earlier design start with a faster ramp-up. With unique new capabilities in placement, optimization, routing, and clocking, the Innovus system features an architecture that accounts for upstream and downstream steps and effects in the design flow. This architecture minimizes design iterations and provides the runtime boost you'll need to get to market faster. Using the Innovus system, you'll be equipped to build integrated, differentiated systems with less risk.

The Innovus system features a variety of key capabilities. Its massively parallel architecture can handle large designs and take advantage of multi-threading on multi-core workstations, as well as distributed processing over networks of computers.

Next-generation slack-driven routing with track-aware timing optimization addresses signal integrity early on and improves post-route correlation. The Innovus system includes full-flow multi-objective technology, which makes concurrent electrical and physical optimization possible. It also shares a customizable flow via a common UI and user commands with synthesis and signoff tools. As a result, you can take advantage of robust reporting and visualization, improving your design efficiency and productivity.

Cadence's Genus™ Synthesis Solution is integrated tightly with the Innovus system, which enables a seamless move from RTL synthesis to netlist. With shared placement technology in the GigaPlace™ tool for physical synthesis, this offers a big benefit for advanced-node design convergence.

Cadence's Tempus™ Timing Signoff Solution, Quantus™ QRC Extraction Solution, and Voltus™ IC Power Integrity Solution are integrated with the Innovus system. With this integration, you can accurately model the parasitics, timing, signal, and power integrity issues at the early stage of physical implementation, and achieve faster convergence on these electrical metrics, resulting in faster design closure.

Block Diagram


  • Massively parallel architecture for handling large designs and supporting multi-threading on multi-core workstations, as well as distributed processing over networks of computers
  • New GigaPlace solver-based placement technology, which is slack driven and topology, pin access, and color aware to provide optimal pipeline placement, wire length, utilization, and PPA
  • Advanced, multi-threaded, layer-aware optimization engine, which is timing and power driven to reduce dynamic and leakage power
  • Additional advanced-node technologies, such as via pillars, IR-aware placement, clock skewing for power, continuous congestion monitoring, and optimized routers for handling self-aligned double patterning for better PPA







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