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Short Description

芯片设计者在传统的电源管理方法上浪费太多的节能机会,因为节能机会很难发现,而且电路状态也不能快速转换到能够节能的级别。能量处理单元(EPU)的ICE-Grain系列利用电路闲置时刻 - 在生产工作不需要电路工作的那段时间 - 使电源状态转换比传统方法快500倍,同时支持无限制的同步功率晶粒切换。

ICE-Grain EPU是管理和控制电路闲置时刻的硬件子系统,可最大限度地降低能耗以及节省功耗。这些EPU是用户自己可配置扩展的,以满足设计规范,同时提供与行业标准EDA环境的自动化RTL和UPF代码生成,验证和设计流程集成。 ICE-Grain EPUs与传统的片上电源管理方法能够共存并且相互操作。

ICE-Grain EPU通过将分布式硬件用于识别闲置和活动时刻,通过功率状态排序以及直接控制功率最小化电路的任务来获得其速度优势。更快的切换允许EPU利用更短的闲置时间并选择更深的功率状态。当设计被划分成许多功率晶粒时,EPU可以并行处理每秒数百万次电源状态转换(MSPS),比使用基于软件的专用微控制器方法高数百倍,同时提供确定性的响应能力。 EPU处理的闲置时间越多,MSPS数越多,芯片上的节能就越多。

ICE-G1,ICE-G3和ICE-P3作为首批实施可重编程的ICE-Grain Power Architecture?的产品,将有源和无源功率节省技术集成到自动化方法中,用户可以通过第一个设计扩展到其他衍生,从而不断完善提取更多的节能。

Overview

Chip designers waste too many energy-saving opportunities with conventional power management approaches because they can t easily expose them, nor transition circuit states fast enough to take advantage of them. The ICE-Grain family of Energy Processing Units (EPUs) exploits circuit idle moments - those periods of time when circuits are not needed for productive work - to make power state transitions up to 500 times faster than conventional approaches while supporting simultaneous switching of an unlimited number of power grains.

ICE-Grain EPUs are hardware subsystems that manage and control circuit idle moments to minimize energy consumption and maximize power savings. These EPUs are user-configurable and scalable to meet design specifications while providing automated RTL and UPF code generation, verification, and design flow integration with industry-standard EDA environments. ICE-Grain EPUs co-exist and interoperate with conventional approaches to on-chip power management.

ICE-Grain EPUs derive their speed advantage by applying distributed hardware to the tasks of identifying idle and active moments, sequencing through power states and directly controlling the power minimization circuits. Faster switching allows the EPU to exploit shorter idle moments and choose deeper power states. When the design is partitioned into many power grains, EPUs scale to process millions of power state transitions per second (MSPS) in parallel, hundreds of times more than software-based approaches leveraging dedicated microcontrollers, while delivering deterministic responsiveness. The more idle moments an EPU processes, the higher the MSPS number and the greater the energy savings on chip.

As the first products implementing the reprogrammable ICE-Grain Power Architecture®, ICE-G1, ICE-G3 and ICE-P3 aggregate both active and static power savings techniques into an automated methodology that users can scale and repeat from their first design to its derivatives to extract more savings through successive refinement.

Block Diagram

Features

  • Maximizes Power Savings Opportunities
    • Distributed architecture and automation enable fine-grained power partitioning to expose idle moments.
    • Aggregation of savings techniques like DVFS, clock/power gating and retention switching ensures minimum energy consumption.
  • Minimizes Energy Consumption
    • Autonomous EPU identifies, sequences, and controls power state transitions up to 500X faster than conventional CPU-based approaches.
    • Distributed power grain and cluster controllers provide parallel operation and deterministic responsiveness.
    • EPU delivers more than 10 MSPS to exploit idle moments and save energy.
  • Adapts to Operating Conditions
    • Reprogrammable architecture supports optimization to varying operating modes.
    • Internal monitors enable observation-driven adaptation to the end system.
  • Automates Energy Control
    • Powerful UI abstracts control complexity into user-defined power states with automated derivation of grain controllers.
    • Imports and exports RTL and IEEE-1801 UPF views to ensure correctness.
  • Speeds Integration
    • Flexible grain controllers adapt to customer-defined clocking, reset, isolation, retention and power gating approaches.
    • Timing-friendly internal signaling simplifies physical implementation.
    • Architecture provides easy interfacing to existing power control implementations.

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