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All Silicon IP

Overview

Power Quencher® LDOs: This series of low-power, fully-integrated low dropout (LDO) voltage regulators achieves a low-noise output voltage without external components, thus saving package pins and valuable PC board space. These LDOs are silicon-proven in the TSMC 40 nm ULP process and are a part of our 40 nm integrated power management unit (PMU) IP core series that has been optimized for integration into Application Specific Integrated Circuits (ASICs) or Systems-on-a-Chip (SoCs), including radio frequency (RF), wireless, and narrowband Internet of Things (NB-IoT) applications.

Tech Specs

FoundryTSMC
Geometry nm40
Target Process NodeTSMC 40

Features

  • Input Power Supply: 2.8 to 4.2 V
  • Output Voltage: 1.1 or 1.85 V (selectable)
  • Maximum Load Current: 3 mA
  • No external components required

Deliverables

  • GDSII
  • Spice Netlist and/or Cadence Schematic
  • IP Datasheet, User', s Guide, and Test Plan
  • Behavioral Model

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