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All Silicon IP

Overview

The DesignWare® Smart Data Fusion IP Subsystem is a complete, pre-verified, hardware and software solution optimized for a wide range of ultra-low power IoT applications. It is designed for fast and easy integration within a larger system context.

The fully configurable Smart Data Fusion IP Subsystem includes the choice of a low gate count and energy-efficient DesignWare ARC® EM5D, EM7D, EM9D or EM11D processor for both RISC and DSP processing, accompanied by an extensive collection of I/O functions and fast math (trigonometric) accelerators. The software libraries of the subsystem contain small-footprint drivers for all I/O, plus DSP functions supporting signal processing. The integrated solution is optimized for "always on" data fusion combining sensor, voice, gesture and basic audio processing typically implemented in IoT edge devices.

Tech Specs

Maturity Available

Features

  • Integrated, pre-verified hardware and software IP subsystem
  • ARC EM processors with cache and DSP extensions deliver extremely low gate count and highly efficient processing performance
  • Extensive library of software DSP functions enable sensor signal processing
  • Hardware accelerators boost performance efficiency and reduce power consumption by up to 85%
  • Configurations consuming <7μW/MHz in a 40-nm process
  • Integrated peripherals provide a wide range of SoC connectivity options for SoC/MCUs

Deliverables

  • IPLib installation file, which includes: User-configurable hardware (RTL) and software source code (using Synopsys', ARChitect IP configuration tool), Complete set of front-end views
  • Demonstration application available as design template, ARC EM IPLib installation file
  • Databook (PDF)
  • Release notes (PDF)
  • ARChitect configuration tool

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