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All Silicon IP

Overview

UHD (4K, 60FPS) resolution targeting WAVE521C is optimally designed and architected to support real-time encoding and decoding of both HEVC and H.264 as a combined IP. By sharing common blocks of HEVC and H.264 codec, the IP architecture becomes streamlined with minimum logics and memories fitting into small sized SoCs. Thereby, SoCs using WAVE521C is perfectly suited for applications requiring high performance with very low power consumption.

Benefits

  • Supported standards
    • HEVC - Main/Main 10 Profile, Level 5.1
    • H.264 - High/High 10 Profile, Level 5.2
  • Codec type
    • ENCODER + DECODER
  • Format
    • 4:2:0, 4:2:2
  • Bit-depth
    • 8-/10-bit
  • Max. resolution
    • 8192 x 8192
  • Performance
    • 4Kp60
  • Bus interface
    • 128-bit AXI / 32-bit APB

Applications

IP Camera, Action Cemera, Smart Security

Block Diagram

Features

  • Frame Buffer Compression
    • Lossless with efficient memory access patterned compression technology
    • Low latency tolerance
  • Frame based processing
    • Promising the lowest burden to host processor for encoding and decoding operation Smart encoding scheme
  • ROI(Region Of Interest) encoding
  • Background detecting

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