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All Silicon IP

Overview

The OL_H264E-CFS core is a hardware implementation of the H.264 video compression algorithm. The core accepts up to the highest resolution HDTV video stream as input and outputs the encoded bitstream. No DRAM required, thanks to the compressed reference frame store technology. Simple, fully synchronous and silicon proven design with low gate count.

Benefits

  • The combination of low gate count, low operating frequency, low power, and full HDTV resolution support makes this core an application-enabling technology.
  • The presence of the CFS with such high compression instead of a standard external reference frame store makes this core unique for its low resource and power requirements. This core is suitable for a wide range of applications including mobile phones, camcorders, webcams and video surveillance cameras.
  • The very small footprint of this core also facilitates novel applications such as its direct integration on to a CMOS sensor. This would create an extremely compact intelligent sensor accepting light directly at its input and outputting an H.264 bitstream.

Applications

  • Digital video recorders
  • Video wireless devices
  • Video surveillance systems
  • Hand held HDTV video cameras

Tech Specs

Maturity Silicon proven

Features

  • Fully compatible with the ITU-T H.264 specification
  • Highly (10-15:1 ) compressed frame store (CFS) with perfect reconstruction (no error/drift) with third party standard decoders. Patented technology
  • Extremely low power : no external DRAM required and much lower bandwidth and power through the CFS
  • I and P frame support
  • Silicon proven in a SoC from a major silicon vendor
  • Profile level 4.1, can be decoded by Baseline, Main or Hi Profile decoder
  • Supports up to the highest HDTV video resolution (1920x1080 @ 30 fps progressive)
  • Very low operational frequency : from ~1.5 MHz for QCIF @ 15 fps to ~250 MHz for 1920x1080 @ 30 fps
  • Single core HDTV support in FPGA : 720p (1280x720) at 30 fps in low end device
  • No CPU required for encoding
  • Constant Bit Rate (CBR). Partial Variable Bit Rate (VBR)
  • Very low latency (~1.1 ms for VGA @ 30 fps)
  • Motion vector up to -16.00/+15.75 pixels around the predicted motion vector (-24.00/+23.75 around the origin), down to quarter pixel
  • Support for most of intra4x4 and all intra16x16 modes
  • Block skipping logic for lower bitrate
  • Supports YUV 4:2:0 video input
  • Min Clock speed = ~ 4 x the raw pixel clock speed
  • Low gate count : 280 Kgates + 217 Kbits of RAM for real time 1080p @ 30
  • Simple, fully synchronous design
  • Available as fully functional and synthesizable VHDL or Verilog soft-core

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