Design & Reuse We Chat
You are here : design-reuse.cn  > Multi Media Vision  > Image
Download Datasheet        Request More Info
All Silicon IP

Short Description

JPEG-LS-E内核实现了符合JPEG-LS,ISO / IEC 14495-1标准的高效,低功耗,无损和接近无损的图像压缩引擎。 基于LOCO-I(LOw COmplexity LOlessless COmpression for Images),JPEG-LS算法在数值上导致无损压缩效率,获得的压缩比类似于或优于JPEG2000等更高级算法所获得的压缩比。由于其较低的计算复杂性和基于行的处理,JPEG-LS还能够实现具有更小硅片尺寸和更低内存要求的硬件实现。此外,JPEG-LS标准的Near-Lossless模式使得更高的压缩比和可视的无损压缩图像成为可能,允许用户设置重构图像与原始图像样本之间的最大可接受差异。 JPEG-LS-E内核在紧凑且易于使用的硬件模块中提供了标准的完整压缩效率。通过标准AMBA®接口与系统的核心接口:通过AXI4-Stream接口接受图像并输出压缩数据,并通过32位APB接口访问其控制和状态寄存器。在寄存器编程后,内核可以编码任意数量的图像,而不需要系统提供任何进一步的帮助或操作。用户可以选择使用专用AXI Streaming接口在压缩流中插入时间戳或其他元数据。 核心采用行业最佳实践设计,其可靠性已通过严格的验证和芯片验证。可交付成果包括完整的验证环境和比特精确的软件模型。 这个核心可以映射到任何Intel,Lattice,MicroSemi或Xilinx可编程器件,或任何ASIC技术,只要有足够的硅资源可用。请联系CAST销售部门,根据您的具体实施要求获取准确的特征数据


The JPEG-LS-E core implements a highly-efficient, low-power, lossless and near-lossless image compression engine that is compliant to the JPEG-LS, ISO/IEC 14495-1 standard.

Based on LOCO-I (LOw COmplexity LOssless COmpression for Images), the JPEG-LS algorithm leads in numerically lossless compression efficiency, attaining compression ratios similar or superior to those obtained with more advanced algorithms such as JPEG2000. JPEG-LS also enables hardware implementations with a much smaller silicon footprint and lower memory requirements, thanks to its lower computational complexity and line-based processing. Further, the Near-Lossless mode of the JPEG-LS standard makes higher compression ratios and visually lossless compressed images feasible, allowing the user to set the maximum acceptable difference between a reconstructed and an original image sample.

The JPEG-LS-E core delivers the full compression efficiency of the standard in a compact and easy-to-use hardware block. The core interfaces to the system via standardized AMBA® interfaces: it accepts images and outputs compressed data via AXI4-Stream interfaces, and provides access to its control and status registers via a 32-bit APB interface. After its registers are programmed, the core can encode an arbitrary number of images without requiring any further assistance or action from the system. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface.

The core is designed with industry best practices, and its reliability has been proven through both rigorous verification and silicon validation. The deliverables include a complete verification environment and a bit-accurate software model.

This core can be mapped to any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements.


The JPEG-LS-E is suitable for systems requiring numerically or visually lossless compression of images or video of potentially high color or greyscale accuracy. Application areas include medical Imaging (DICOM), aerospace imaging or surveillance, and advanced driver assistance systems.

Block Diagram


  • Highly Efficient Numerically Lossless Compression
    • Better compression ratio than most lossless compression algorithms (JPEG2000, PNG, etc.)
  • Near-Lossless Compression
    • Enables greater compression with visually lossless quality by constraining the maximum difference between reconstructed and original image samples
  • Maximum image resolution of 64Kx64K, or higher with via support for oversize image dimension parameters
  • Up to 16 bits per color sample; up to four color components

Easy to Use and Integrate

  • Run-time programmable input and encoding parameters
    • Image resolution, number of color components, color depth
    • Maximum reconstruction error, Point-Transform, Local Gradient, Reset Frequency
  • Automatic program-once encode-many operation
  • AXI4-Stream interfaces for image and compressed data, and 32-bit wide APB for register access
  • Dedicated, easy-to-use timestamps interface


  • Source code RTL (Verilog) or Targeted FPGA Netlist

  • Bit Accurate Model

  • Sample simulation and synthesis scripts

  • Verification testbenches

  • Comprehensive documentation








© 2018 Design And Reuse


不得复制,重发, 转载或以其他方式使用。