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All Silicon IP


Minima Dynamic Margining is a unique sub-system IP approach to near-threshold voltage design. It allows the device to modify power usage during operation in response to performance needs, process variations and environmental conditions in real time. Ultra-Wide Dynamic Voltage and Frequency Scaling (UW-DVFS) enables low-power operation to take place at the lowest possible voltage in any given task, data or ambient condition, operating reliably even at near threshold voltages allowing minimum energy operation. The solution combines hardware and software to provide Dynamic Margining capabilities for any digital logic.

Minima sub-system IP is process and EDA -tool agnostic, easy to integrate to virtually any pipelined logic and can be tailored to fulfill customer application specific needs. It targets Ultra-Low Power MCUs like Arm Cortex-M series (M0 to M4), NXP Coolflux DSP -family and Tensilica DSP's.

Due the Minima Processor patented and silicon proven near-threshold voltage methodology, it's possible to achieve even 15x energy efficiency in any digital logic.


  • Allows any logic / processor / DSP to operate at ultra-low voltage
  • Up to 15x in energy improvement
  • Ultra-wide DVFS enables lowest possible energy consumption for every application purpose
  • Faster Time-To-Market
  • Process agnostic
  • Completely mainstream EDA compatible
  • Covered by multiple patents in the area of energy consumption minimizing in SoC designs


  • Ultra-wide Dynamic Voltage and Frequency scaling
  • Patented Dynamic Margining IP enables optimal energy/MHz for every application purpose
  • Minimum Energy Operation at Near-Threshold Voltage
  • Synchronous operation








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