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All Silicon IP

Overview

AndesCore™ N22 is a 32-bit 2-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications that require low energy consumption and small area. It is compliant to RISC-V technology with several efficient performance features, including simple dynamic branch prediction, instruction cache, and local memories. It supports 32 or 16 general purpose registers (GPRs) and fast or small multiplier for performance/area tradeoff. In addition, it comes with rich optional features to ease SoC integration such as vectored CLIC and PLIC for design flexibility, AHB-Lite 32-bit bus for system integration, Fast I/O interface for low latency accesses, APB for CPU local peripherals, PowerBrake and WFI/WFE mode for low power and power management, and JTAG debug interface for development support.

Applications

  • Sensor fusion
  • Smart Meter
  • Small IoT devices
  • Wearable devices
  • Toy and electronic education equipment

Block Diagram

Features

  • AndeStar™ V5/V5e Instruction Set Architecture (ISA), compliant to RISC-V technology
  • Support RV32IMAC/EMAC
  • Andes extensions, architected for performance and functionality enhancements
  • 32-bit, 2-stage pipeline CPU architecture
  • 16/32-bit mixable instruction format for compacting code density
  • Branch predication to speed up control code
  • Configurable Multipiler
  • Physical Memory Protection (PMP)
  • Core-Local Interrupt Controller (CLIC) with selective vectoring and priority preemption 
  • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting SoC with multiple processors 
  • Advanced CoDense™ technology to reduce program code size
  • StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
  • Several configurations to tradeoff between core size and performance requirements

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