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Short Description

EFLX4K eFPGA IP内核(包括Logic和DSP版本)已在TSMC16FFC上完全验证。 GDS还与TSMC16FF/12FFC +兼容,无需更改,只需重新定时。台积电12FFC也是如此。

目前,评估板可以集成EFLX200K验证芯片(7x7阵列的EFLX 4K内核:182K LUT4,560 MAC,1.4Mbit附加SRAM,PLL和PVT),以便客户在真实芯片上测试其RTL。 客户可以免费使用电路板进行短期评估,也可以购买电路板。 评估板附带文档,示例和测试台。


The EFLX4K eFPGA IP core, both the Logic and DSP versions, have been fully validated on TSMC16FFC. The GDS is also compatible with TSMC16FF+ with no change, just retiming. Same for TSMC12FFC.

Evaluation boards are available now that integrate the EFLX200K validation chip (a 7x7 array of EFLX 4K cores: 182K LUT4, 560 MACs, 1.4Mbit attached SRAM, PLL & PVT) for customers to test their RTL on real silicon. Customers can either use the boards at no cost for short-term evaluation or can purchase boards. The evaluation board comes with documentation, examples, and test benches.

Contact info@flex-logix.com for more information on obtaining an evaluation board for evaluation or purchase.

Block Diagram

Tech Specs

Target Process NodeTSMC 16FF+ / TSMC 12 FFC


The EFLX150 Logic Core and EFLX4K Logic and DSP cores in TSMC 16FF+/FFC/12FFC use our latest Gen 2 architecture with the following improvements (ALL future EFLX implementations will also be Gen 2 ):

  • Improved, higher performance XFLX™ interconnect, especially for larger arrays
  • 6-input LUTs with Dual Outputs with 2 optional flip flops (can also be dual 5-input LUTs) - higher logic density and higher performance due to fewer LUT stages
  • The Gen 2 combination of the improved interconnect and wider LUTs results in ~20-30% reduction in LUTs required and ~25% improvement in critical path performance compared to the first generation dual-4-input-LUTs in the same process node. A LUT6 has 1.6x the logic capacity of a single LUT4. Read here why 6-input LUTs give higher performance and higher density.
  • In the EFLX4K DSP cores, the MACs are pipelined 10 in a row (compared to 5 in Gen 1) enabling higher performance for FIR/IIR filters, etc by using high speed data pipelining rather than using the general programmable interconnect network
  • DFT is enhanced to provide >98% coverage of all stuck-at faults with significantly higher coverage achieved with larger test vector sets, which Flex Logix provides.
  • Test time for the Gen 2 architecture is enhanced with new parallel load logic which reduces test time by ~100x compared to the first generation
  • Readback circuitry (EFLX4K TSMC 16FFC/FF+ and all future implementations) enables configuration bits to be read back and checked for soft errors (and corrected) as frequently as desired to improve reliability for High-Rel applications like automotive and defense/aerospace








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