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All Silicon IP

Short Description

标函数库,可以快速组合和配置,以创建自定义AI算法加速器。通过使用Design Profiler和AI Engine Explorer,eSilicon开发的和第三方IP可以被配置为AI tile通过ASIC机箱构建器,可以对各种候选架构进行早期功耗,性能和面积(PPA)分析。 neuASIC平台还使用复杂的知识库来确保最佳的PPA。 neuASIC IP库的元素包含大多数AI设计中的功能,从而形成了核心架构,该架构在AI算法更改方面既优化又耐用。特定的算法修改可以通过结合适当的AI 瓦片的次要芯片修订的组合来适应,或修改2.5D软件包以集成适当的内存组件。 eSilicon开发的针对AI的“瓷砖”包括诸如卷积引擎之类的子系统,其具有与为AI优化的存储器子系统紧密耦合的MAC块,有着最低的面积和功率。针对跨存储器子系统的数据传输开发了特殊的创新结构。它还包括转置存储器等。 HBM存储器堆栈的物理接口(PHY)也是库的一部分。 eSilicon大约有100名工程师正在研究这种AI IP的设计和硅强化。


Through customized, targeted IP offered in 7nm FinFET technology and a modular design methodology, the neuASIC platform removes the restrictions imposed by changing AI algorithms. The platform includes a library of AI-targeted functions that can be quickly combined and configured to create custom AI algorithm accelerators. With the use of a Design Profiler and AI Engine Explorer, eSilicon-developed and third-party IP can be configured as AI "tiles" via an ASIC Chassis Builder, allowing early power, performance and area (PPA) analysis of various candidate architectures. The neuASIC platform also uses a sophisticated knowledge base to ensure optimal PPA.

The elements of neuASIC IP library include functions that are found in most AI designs, resulting in a core architecture that is both optimized and durable with respect to AI algorithm changes. Specific algorithm modifications can be accommodated through a combination of minor chip revisions that integrate appropriate AI "tiles" or modifications of the 2.5D package to integrate appropriate memory components.

eSilicon-developed AI-targeted "tiles" include subsystems such as convolution engines that have MAC blocks tightly coupled with memory subsystems optimized for AI that result in lowest area and power. Special innovative structures have been developed for data transfer across memory subsystems. It also includes transpose memory, among others. The physical interface (PHY) to the HBM memory stack is also part of the library. Approximately 100 engineers at eSilicon are working on the design and silicon hardening of this AI IP.

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