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Short Description

RivieraWaves蓝牙IP系列涵盖蓝牙低功耗(BLE),蓝牙双模(BTDM)和蓝牙标准(BT2.1 + EDR)。 随着蓝牙标准发展到蓝牙5,高级功能和低功耗仍然是平台的核心。RivieraWaves蓝牙IP平台由硬件基带控制器和功能丰富的软件协议栈组成。 对于蓝牙低功耗,此协议栈包含链路层直至GAP / GATT以及全套服务和配置文件。

Overview

The RivieraWaves Bluetooth IP family covers Bluetooth low energy (BLE), Bluetooth dual mode (BTDM) and Bluetooth Classic (BT2.1+EDR). Advanced features coupled with low power remain at the heart of the platforms as the Bluetooth standard evolves to Bluetooth 5.
The RivieraWaves Bluetooth IP platforms consist of a hardware baseband controller, plus a feature-rich software protocol stack. For Bluetooth low energy, this protocol stack encompasses the Link Layer up to the GAP/GATT plus a comprehensive set of Services and Profiles. For Bluetooth dual mode, this protocol stack presents an industry standard HCI interface. A flexible radio interface allows the platform to be deployed with either RivieraWaves RF or various partners RF IP, enabling optimal selection of foundry and process node.
The software stack is easily portable to the customer s choice of embedded processor, such as the CEVA-TeakLite-4, ARM Cortex-Mseries, ARC EM family, AndesCore family, Cortus APS family and others.
The Bluetooth IPs are provided with an optional FPGA platform plus a comprehensive GUI validation tool for manual testing and automatic execution of test scripts for laboratory testing.
The RivieraWaves Bluetooth platforms are complemented in many applications by CEVA s extensive portfolio of audio/voice solutions and Always-On sensor hub solutions, based around the CEVA-TeakLite-4 DSP core.

Block Diagram

Features

This provides a very low power, low MIPs & low gate count platform for applications requiring single mode Bluetooth Low Energy (BLE), e.g. smartwatches, hearing aids, wearable sensors for medical /sports (heart rate, glucose, temperature), remote controls, toys, environment sensors, location beacons and many other Internet of Things applications. The hardware baseband controller is provided as a Verilog IP package. It performs packet encoding/decoding and frame scheduling and is complemented by a hardware AES128 encryption engine. The software stack is provided as a C code IP package. It consists of Link Layer (LL), L2CAP, ATT, SMP, GAP/GATT, services and profiles.

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