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All Silicon IP


SonicsExpress provides a high bandwidth bridge between two clock domains, with optional voltage domain isolation. SonicsExpress supports AXI or OCP protocols and is capable of crossing clock boundaries, power boundaries, and large spans of physical distance. In addition, SonicsExpress is optimized for high-bandwidth, low-latency communication. SonicsExpress maintains transaction integrity for any ratio of initiator and target port clock frequencies. The bridge permits full peak bandwidth utilization on both ports and maintains sustainable bandwidth utilization on the fast port that matches the peak bandwidth available on the slow port. Designed to support both single threaded and multi-threaded configurations, SonicsExpress allows multi-threaded bridges to be configured to operate in either blocking or non-blocking mode. In addition, the thresholds for blocking behavior can be set to make it statistically unlikely to occur. Since clock boundary crossings often coincide with power domain crossings, tactical cells instantiated on the signals that cross the asynchronous boundary address voltage level shifting and isolation. Tactical cells allow these blocks to be mapped to their own technology library. While maintaining good synchronous design practices such as qualifying all vectors with validity handshaking protocols, SonicsExpress minimizes fall-through latency for an asynchronous crossing. All handshaking signals are driven directly from flops to avoid hazard switching and all handshake type signals being received across the asynchronous boundary are double-rank synchronized to minimize the likelihood of metastability. All signals that are not double-rank synchronized are registered immediately in the receiving domain to minimize and localize false timing paths that might complicate synthesis and test. Only the rising edges of clocks are used.

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