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Overview

With the ICE-Grain Power Architecture, SoC designers partition their chips into much finer grains , which enables up to 10x faster and more precise power control. Power grains are very small sections of an SoC that include functional logic that can be individually power controlled using one or more savings methods. A grain is connected to one or more clock domains and attached to at least one power domain, and includes defined signals and conditions for power control. Grains are often an order of magnitude smaller than conventionally independent power or clocking domains, and multiple grains can be composed into larger hierarchical grains. The ICE-Grain Power Architecture automates the tasks of grain connection and management by synthesizing both central and local control circuitry blocks for the greatest total SoC power reduction.

Benefits

  • Supports fine-grain power partitioning with autonomous control
  • Saves more power than conventional software approaches
  • Makes highly sophisticated power management techniques easy to adopt in a complete subsystem solution

Block Diagram

Features

  • The first commercial technology to manage and control all common power techniques in a unified environment.
    • Hardware identification of power saving opportunities
    • Unique wake on demand technique allows automated grain shut down and instantaneous wake up when needed
    • Hardware control of clock, isolation, retention, and power gating sequences
    • Hardware control of operating points for DVFS (dynamic voltage and frequency scaling) and AVS (adaptive voltage scaling)
    • Leverages existing software-controlled power management techniques
  • Scalable, distributed, and modular architecture.
    • Centralized grain controller block manages individual and inter-grain power sequencing and operating point assignment
    • Distributed, local controller blocks per grain handle power sequence execution and minimize the logic in the always on domain
    • Hardware event control system supports hundreds of grains with predictable, low latency and virtually no impact on processor performance
  • Easy, worry-free implementation of hardware control and fine-grain power reduction.
    • Scales to support hundreds of power grains that are correct-by-construction and include on-chip debug and monitoring
    • Minimal area and power impact to the original design
  • EDA tool support complies with industry-standard tools, flows, and formats.
  • Complete, integrated solution; no special power expertise required.
    • With the ICE-Grain Power Architecture, designers work at the highest level of abstraction, which means they do not have to be power management experts to adopt and use the solution.
    • Leverages existing power management techniques where designers can integrate some or all of their existing software-based approach

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