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MemMax AMP is an intelligent Dynamic Random Access Memory scheduler designed for use with any AMBA AXI compliant bus fabric and memory controller. Ideal for high-bandwidth applications, MemMax AMP offers a sophisticated QoS scheduler based on AXI IDs and advanced arbitration schemes in order to guarantee memory bandwidth efficiency. By decoupling the dependencies of the AXI-based SoC from the DRAM subsystem, MemMax AMP encourages the selection of DRAM technology that offers the best cost and performance value for each individual application. In addition, MemMax AMP provides memory efficiencies beyond those traditionally achievable with simple scheduler or controller solutions alone. These increased efficiencies result in cost benefits for SoC integrators, who can use less raw DRAM bandwidth in their systems, and thereby reduce pin-count, chip-count or speed grade of DRAM. MemMax AMP implements a variety of complex Quality-of-Service (QoS) mechanisms designed to ensure low latency on priority traffic and low jitter on controlled bandwidth traffic. A traffic flow within MemMax AMP can be programmed to be one of three QoS modes: Priority, Controlled Bandwidth, or Best Effort. MemMax AMP schedules transactions from priority traffic ahead of the controlled bandwidth traffic, which is given preference over best effort traffic. One set of read and write queues is dedicated to CPU traffic to minimize the effect of requests from other masters. In addition to the different QoS precedence modes, MemMax AMP also maintains a running credit counter to make sure that each traffic flow is serviced in accordance with its requested bandwidth, thereby maintaining fairness among the different flows.


  • Amplifies SoC DRAM Performance
    • High-speed scheduler allows for silicon frequency of up to 533MHz (in TSMC 65nm GP libraries) to support up to DDR2-1066 or DDR3-1600
    • Support for Fixed, INCR and WRAP burst types
    • Support for 4 or 8 bank DRAM systems
  • Lowers SoC and System Costs Through Improved Memory Bandwidth Efficiency
    • Up to 85% efficiencies possible
  • Shortens Time-to-Market
    • DRAM technology selection (DDR2, DDR3 etc.) decoupled from the rest of the SoC
    • Flexible architecture enables easy Plug-and-Play and performance scalability without redesign of memory subsystem
  • Improves Quality-of-Service (QoS)
    • Dedicated CPU queues for improved latency control
    • Performs dynamic priority management among independent queues to ensure predictable memory performance
    • Allows runtime programmability of QoS modes
    • Performs careful trade-off between memory efficiency requirements and bandwidth/latency requirements








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