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Overview

As SoC complexity grows, a major design challenge is achieving highly sustainable bandwidth when accessing shared memory. MemMax DRAM system, integrates Sonics innovative MemMax Scheduler and Synopsys DesignWare DDR Protocol Controller IP, to offer designers a plug and play solution enabling the rapid construction of a high performance SoC external DDR2/3 memory subsystem. Pre-verified interface logic and configuration settings for both the MemMax Scheduler and the Synopsys Protocol Controller are included as part of the MemMax DRAM System solution. These additions are specifically engineered to operate the Universal DDR Protocol Controller at its optimal performance, providing an out of the box alternative to spending extensive engineering time and effort assembling and optimizing similar components. When used in conjunction with Sonics line of on-chip networking solutions, the MemMax DRAM System provides a highly optimized processor to memory pins SoC architecture that meets even the most demanding communications and streaming bandwidth intensive applications, such as high definition TV or state-of-the-art set top boxes. Using the MemMax DRAM System improves DRAM utilization by providing Quality of Service (QoS) guarantees to heterogeneous processing elements, lowering the risk of starving processing elements such as DSPs, H.264 devices, and graphics processors. The MemMax DRAM System manages and schedules multi-threaded pipelined accesses to DRAM to improve memory utilization and effective bandwidth. To reduce total SoC die area and lowers overall power consumption, designers can use compiled RAM to consolidate all of the flip-flop based buffers normally distributed among the various initiator cores into a single buffer within the memory subsystem.

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